Ascatron has a solid competence in key processes for the manufacturing of SiC semiconductors and devices for power electronics like JFET and MOSFET transistors, as well as Schottky-, JBS-, and PiN-diodes. Our fabrication processes can also be applied to other applications like sensors for exhaust gases, UV detection, or pressure measurement.
SiC Process Modules
Our SiC fabrication is based on stable unit process modules that are combined and adjusted according to the specific device design:
- Advanced SiC Epitaxy Multilayer pn-junctions & embedded structures
- Reproducible Lithography Automatic photo-resist processing & 0.5 µm stepper
- Deep Trench Etching Precise side-wall control for void-free re-growth
- Oxidation development Combining deposition and thermal anneal
- Advance Metallisation Wide range of metal and passivation combinations
SiC Device Technologies
Ascatron offers a number of power device technologies as the basis for the custom specific device design. The process can be optimized to meet the specific requirements, e.g. packaging compatible metallisation.
- Schottky diode For material evaluation
- JBS diode Both implanted and epitaxial 3DSiC concepts
- HV-PiN diode Epitaxial grown anode and pn-junction grown in one run
- Vertical DMOSFET Advanced gate oxide technology using deposited oxides
- Epitaxial buried grid JFET Based on embedded epitaxial technology
Ascatron Unique Technologies
Ascatron offers special process and design solutions to improve the performance of the customer device:
The Ascatron Epitaxial PN Schottky diode (EPS) technology is based on a proprietary concept utilizing a buried grid as junction barrier. The important function of the buried grid is the reduction of the leakage current due to efficient reduction of the surface field under the Schottky contact. This gives 3 orders of magnitude lower leakage current compared to the conventional JBS surface grid design, thus allowing increasing the max operation temperature from 175°C up to 250°C. Ascatron offers customized fabrication of 1200V EPS diodes. We are currently developing the device technology for 1700V and 3,3 kV devices.
SiC epitaxial buffer technology
To reduce defects penetrating from the substrate into the device epilayers designed to sustain high blocking voltages and handling high current densities. Prominent examples are the basal plain dislocations causing forward voltage drop degradation in bipolar devices. Another example is stacking fault defects in cubic SiC (3C-SiC). With our buffer technology we can keep the stacking faults in the substrate, where they do no harm, and prevent them from penetrating into the n-drift layer.
3D structured SiC epitaxial technology (3DSiC)
Including re-growth on non-planar surfaces and growth of embedded structures to form damage free, active device areas with well controlled doping concentrations in a wide range. Our epitaxial technology enables device designs not in compliance with standard growth processes and improves the device performance especially for high temperature operation. Our growth technology has been applied to an all epitaxial buried grid high performance normally-off JFET switch.
3C-SiC process technology
To enable for example the design of power MOSFETs with high channel mobility and blocking voltages up to 1000 V. Interesting applications are compact switch mode power supplies and high temperature electronics. The technology is scalable to large diameter wafers required to target high volume consumer electronic applications. 3C-MOSFETs are thus an interesting alternative to super-junction silicon MOSFETs and the emerging GaN technology.